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CYFB0072V 72-mbit video frame buffer cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 001-88646 rev. *a revised september 26, 2013 72-mbit video frame buffer features memory organization ? density: 72-mbit ? organization: 36 up to 133-mhz clock operation [1] unidirectional operation independent read and write ports ? supports simultaneous read and write operations ? reads and writes operate on independent clocks, upto a maximum ratio of two, enabling data buffering across clock domains. ? supports multiple i/o voltage standard: low voltage complementary metal oxide semiconductor (lvcmos) 3.3 v and 1.8 v voltage standards. input and output enable control for write mask and read skip operations empty & full status flags flow-through mailbox register to send data from input to output port, bypassing the frame buffer separate serial clock (sclk) input for serial programming of configuration registers master reset to clear entire frame buffer partial reset to clear data but retain programmable settings joint test action group (jtag) port provided for boundary scan function industrial temperature range: ?40 c to +85 c functional description the video frame buffer is a 72-mbit memory device which operates as a fifo with a bus width of 36 bits. it has independent read and write ports, which can be clocked up to 133 mhz. the bus size of 36 bits enables a data throughput of 4.8 gbps. the device also offers a simple and easy-to-use interface to reduce implementation and debugging efforts, improve time-to-market, and reduce engineering costs. this makes it an ideal memory choice for a wide range of applications including video and image processing or any system that needs buffering at high speeds across different clock domains. the functionality of the video fram e buffer is such that the data is read out of the read port in the same sequence in which it was written into the write port. if writes and inputs are enabled (wen & ie ), data on the write port gets written into the device at the rising edge of write clock. enabling reads and outputs (ren & oe ) fetches data on the read port at every rising edge of read clock. both reads and writes can occur simultaneously at different speeds provided the ra tio between read and write clock is in the range of 0.5 to 2. a ppropriate flags are set whenever the device is empty or full. the device also supports a flow-through mailbox register to bypass the frame buffer memory note 1. for device operating at 150 mhz, contact sales.
CYFB0072V document number: 001-88646 rev. *a page 2 of 27 logic block diagram write pointer write control logic reset pointer jtag control memory array 72-mbit output register input register configuration registers/mailbox flag logic read pointer read control logic q[35:0] oe rclk ren dval ef ff mb spi_si ld spi_sen spi_sclk d[35:0] ie wen wclk mrs prs tck trst tms tdo tdi
CYFB0072V document number: 001-88646 rev. *a page 3 of 27 contents pin configuration ............................................................. 4 pin definitions .................................................................. 5 architecture ...................................................................... 7 reset logic ................................................................. 7 data valid signal (dval) .............................................. 7 write mask and read skip oper ation ........... .............. 7 flow-through mailbox register .................................... 7 flag operation ............................................................. 7 programming configuration registers ........................ 8 width expansion configuration ............ .............. ....... 11 power up ................................................................... 11 read/write clock requirements ............................... 11 jtag operation ........................................................ 12 maximum ratings ........................................................... 13 operating range ............................................................. 13 recommended dc operating conditions .................... 13 electrical characteristics ............................................... 13 i/o characteristics .......................................................... 14 latency table .................................................................. 14 ac test load conditions ............................................... 15 switching characteristics .............................................. 16 switching waveforms .................................................... 17 ordering information ...................................................... 23 ordering code definitions ..... .................................... 23 package diagram ............................................................ 24 acronyms ........................................................................ 25 document conventions ................................................. 25 units of measure ....................................................... 25 document history page ................................................. 26 sales, solutions, and legal information ...................... 27 worldwide sales and design s upport ......... .............. 27 products .................................................................... 27 psoc? solutions ...................................................... 27 cypress developer community ................................. 27 technical support ................. .................................... 27
CYFB0072V document number: 001-88646 rev. *a page 4 of 27 pin configuration figure 1. 209-ball fbga pinout (top view) 1 2 3 4 5 6 7 8 9 10 11 aff d0 d1 dnu v pu v pu dnu dnu v pd q0 q1 bef d2 d3 dnu dnu v pu dnu dnu ren q2 q3 cd4 d5 wen dnu v cc1 dnu v cc1 dnu rclk q4 q5 dd6 d7 v ss v cc1 dnu ld dnu v cc1 vss q6 q7 ed8 d9 v cc2 v cc2 v ccio v ccio v ccio v cc2 v cc2 q8 q9 fd10 d11 v ss v ss v ss dnu v ss v ss v ss q10 q11 gd12 d13 v cc2 v cc2 v ccio v cc1 v ccio v cc2 v cc2 q12 q13 hd14 d15 v ss v ss v ss v cc1 v ss v ss v ss q14 q15 jd16 d17 v cc2 v cc2 v ccio v cc1 v ccio v cc2 v cc2 q16 q17 k dnu dnu wclk dnu v ss ie v ss dnu v ccio v ccio v ccio ld18 d19 v cc2 v cc2 v ccio v cc1 v ccio v cc2 v cc2 q18 q19 md20 d21 v ss v ss v ss v cc1 v ss v ss v ss q20 q21 nd22 d23 v cc2 v cc2 v ccio v cc1 v ccio v cc2 v cc2 q22 q23 pd24 d25 v ss v ss v ss spi_sen v ss v ss v ss q24 q25 rd26 d27 v cc2 v cc2 v ccio v ccio v ccio v cc2 v cc2 q26 q27 td28 d29 v ss v cc1 v cc1 spi_si v cc1 v cc1 v ss q28 q29 udval dnu d30 d31 prs dnu [2] spi_sclk v ref oe q30 q31 v dnu dnu d32 d33 dnu mrs mb dnu v pd q32 q33 w tdo dnu d34 d35 tdi trst tms tck dnu q34 q35 notes 2. this pin should be tied to v ss preferably or can be left floating to ensure normal operation.
CYFB0072V document number: 001-88646 rev. *a page 5 of 27 pin definitions pin name i/o pin description mrs input master reset: mrs initializes the internal read and write pointers to zero, resets both flags and sets the output register to all zeroes. during master reset, the configuration registers are set to default values. prs input partial reset: prs initializes the internal read and write pointers to zero, resets both flags and sets the output register to all zeroes. during partial reset, the configuration register settings are retained. wclk input write clock: the rising edge clocks data into the frame buffer when writes are enabled (wen asserted). data is written into the buffer memory when ld is high and into configuration registers when ld is low. ld input load: when ld is low, d[7:0] (q[7:0]) are written (read) into (from) the configuration registers. when ld is high, d[35:0] (q[35:0]) are writt en (read) into (from) the buffer memory. wen input write enable: control signal to enable writes to the device. when wen is low data present on the inputs is written to the buffer memory or configur ation registers on every rising edge of wclk. ie input input enable: ie is the data input enable signal that controls the enabling and disabling of the 36-bit data input pins. if it is enabled, data on input pins is written into the frame buffer memory or configuration registers. the internal write address pointer is always incremented at rising edge of wclk if wen is enabled, regardless of the ie level. this is used for 'write masking' or incrementing the write pointer without writing into a location. d[35:0] input data inputs: data inputs for a 36-bit bus. rclk input read clock: the rising edge initiates a read from the frame buffer when reads are enabled (ren asserted). data is read from the buffer memory when ld is high & from the configuration registers if ld is low. ren input read enable: control signal to en able reads from the device. when ren is low data is read from the buffer memory or configuration re gisters on every rising edge of rclk. oe input output enable: when oe is low, device data outputs are enabled; when oe is high, the device?s outputs are in high z (high impedance) state. q[35:0] output data outputs: da ta outputs for a 36-bit bus. dval output data valid: active low data valid signal to indicate valid data on q[35:0]. mb input mailbox: when asserted the reads and wr ites happen to flow-through mailbox register. ef output empty flag: when ef is low, the frame buffer is empty. ef is synchronized to rclk. ff output full flag: when ff is low, the frame buffer is full. ff is synchronized to wclk. spi_sclk input serial clock: a rising edge on spi_sclk clocks the serial data pres ent on the spi_si input into the configuration registers if spi_sen is enabled. spi_si input serial input: serial input data in spi mode. spi_sen input serial enable: enables serial loading of configuration registers. tck input test clock (tck) pin for jtag. trst input reset pin for jtag. tms input test mode select (tms) pin for jtag. tdi input test data in (tdi) pin for jtag. tdo output test data out (tdo) pin for jtag. v ref input reference reference voltage: reference voltage (regardless of i/o standard used) v cc1 power supply core voltage supply 1: 1.8 v supply voltage
CYFB0072V document number: 001-88646 rev. *a page 6 of 27 v cc2 power supply core voltage supply 2: 1.5 v supply voltage v ccio power supply supply for i/os v ss [3] ground ground v pu cmos voltage level the pins a5, a6 and b6 of the fbga pins are requir ed to be pulled up to the cmos voltage level. these pins should be powered up post the power supply v cc1 & v cc2 , and should be stable prior mrst operation. dnu ? do not use: these pins need to be left floating. v pd [3] input connect to gnd (short to v ss ). pin definitions (continued) pin name i/o pin description note 3. all v ss pins should be connected to the same ground plane.
CYFB0072V document number: 001-88646 rev. *a page 7 of 27 architecture the video frame buffer consists of a memory array of 72-mbit along with the logic blocks to implement fifo functionality and its associated features that are built around this memory array. the input and output data buses have a maximum width of 36 bits. the input data bus goes to an input register and the data flow from the input register to the memory is controlled by the write control logic. the inputs to the write logic block are wclk, wen and ie . when the writes are enabled through wen and if the inputs are enabled by ie , then the data on the input bus is written into the memory array at the rising edge of wclk. this also increments the write pointer . enabling writes but disabling the data input pins through ie only, increments the write pointer without doing any writes or altering the contents of the memory location. similarly, the output register is connected to the data output bus. transfer of contents from the memory to the output register is controlled by the read control logic. the inputs to the read control logic include rclk, ren , oe . when reads are enabled by ren and outputs are enabled using oe , the data from the memory pointed by the read pointer is tr ansferred to the output data bus at the rising edge of rclk along with active low dval . if the outputs are disabled but the reads enabled, the outputs are in high impedance state, but internal ly the read pointer is incre- mented. during write operation, the number of writes performed is always an even number (i.e., minimu m write burst length is two and number of writes always a multiple of two), whereas during read operation, the number of reads performed can be even or odd (i.e., minimum read burst length is one). reset logic the frame buffer can be reset in two ways: master reset (mrs ) and partial reset (prs ). the mrs initializes the read and write pointers to zero and sets the output register to all zeroes. it also resets empty flag, full flag & the configuration registers to their default values. a master reset is required after power-up before accessing the frame buffer. prs resets the read pointer, writ e pointer to the first physical location in the memory array. it also resets the flags to their default values. prs does not affect the programmed configuration register values. data valid signal (dval ) data valid (dval ) is an active low signal, synchronized to rclk and is provided to check for valid data on the output bus. when a read operation is performed, the dval signal goes low along with output data. this helps us er to capture the data without keeping track of ren to data output latency. this signal also helps when write and read operations are performed continuously at different frequencies by indicating when valid data is available at the output port q[35:0]. write mask and read skip operation as mentioned in architecture on page 7 , enabling writes but disabling the inputs (ie high) increments the write pointer without doing any write operations or altering the contents of the location. this feature is called write mask and allows user to move the write pointer without actually writin g to the locations. this ?write masking? ability is useful in some video applications such as picture in picture (pip). similarly, during a read operation, if the outputs are disabled by keeping the oe high, the read data does not appear on the output bus; however, the read pointer is incremented. this feature is referred to as a read skip operation. flow-through mailbox register this feature transfers data from input to output directly bypassing the sequential buffer memory. when mb signal is asserted the data present in d[35:0] will be available at q[35:0] after two wclk cycles. normal read and writ e operations are not allowed during flow-through mailbox operation. before starting flow-through mailbox operation reads should be completed to make data valid dval high to avoid data loss from buffer memory. flag operation this device provides two flag pins to indicate the condition of the video frame buffer. full flag the full flag (ff ) operates on double word (burst length of two) boundaries and goes low when the device is full. write operations are inhibited whenever ff is low regardless of the state of wen . ff is synchronized to wclk, that is, it is exclusively updated by each rising edge of wclk. the worst case assertion latency for full flag is four. as the user cannot know that the frame buffer is full for four clock cycles, it is possible that user continues writing data during this time. in this case, the four data words written will be stored to prevent data loss and these words have to be read back in order for full flag to get de-asserted. the minimum number of reads required to de-assert full-flag is two and the maximum number of reads required to de-assert full flag is six. the latency associated with full flag is explained in latency table on page 14 . empty flag the empty flag (ef ) deassertion depends on burst writes and goes low when the device is empty. read operations are inhibited whenever ef is low, regardless of the state of ren . ef is synchronized to rclk, that is, it is exclusively updated by each rising edge of rclk. t he latency associated with empty flag is explained in latency table on page 14 .
CYFB0072V document number: 001-88646 rev. *a page 8 of 27 programming configuration registers the CYFB0072V has ten 8-bit user configurable registers. the tenth register is the fast clk bi t which indicates the faster clock domain. this register can be programm ed in one of two ways: serial loading or parallel loading method. the loading method is selected using the spi_sen (serial enable) pin. a low on the spi_sen selects the serial method for writing into the register. for serial programming, there is a separate sclk and a serial input (si). in parallel mode, a low on the load (ld ) pin causes the write and read operation to these registers. when ld is held low, write and read operations happen sequentially from the first location (0x1) to the last location (0xa). if ld is high, the writes occur to the fifo. register values can be read through the parallel output port regardless of the programming mode selected (serial or parallel). register values cannot be read serially. the registers may be programmed (and reprogrammed) any time after master reset, regardless of whether serial or parallel programming is selected. see ta b l e 1 and table 2 on page 9 for access to configuration registers in serial and parallel modes. in parallel mode, the read and write operations loop back when the maximum address location of the configuration registers is reached. simultaneous read and write operations should be avoided on the configuration registers. table 1. configuration registers addr configuration register default bit [7] bit [6] bit [5] bit [4] bit [3] bit [2] bit [1] bit [0] 0x1 reserved 0x00 x x x x x x x x 0x2 reserved 0x00 x x x x x x x x 0x3 reserved 0x00 x x x x x x x x 0x4 reserved 0x7f x x x x x x x x 0x5 reserved 0x00 x x x x x x x x 0x6 reserved 0x00 x x x x x x x x 0x7 reserved 0x7f x x x x x x x x 0x8 reserved 0x00 x x x x x x x x 0x9 reserved 0x00 x x x x x x x x 0xa fast clk bit register 1xxxxxxxb fast clk bit xx x x x x x
CYFB0072V document number: 001-88646 rev. *a page 9 of 27 table 2. writing and reading configuration registers in parallel mode spi_sen ld wen ren wclk rclk spi_sclk operation 1001 ? first rising edge because both ld and wen are low x x parallel write to first register 1001 ? second rising edge x x parallel write to second register 1001 ? third rising edge x x parallel write to third register 1001 ? fourth rising edge x x parallel write to fourth register 1001 ?? xx ?? 1001 ?? xx ?? 1001 ?? xx ?? 1001 ? tenth rising edge x x parallel write to tenth register 1001 ? eleventh rising edge x x parallel write to first register (roll back) 1010 x ? first rising edge since both ld and ren are low x parallel read from first register 1010 x ? second rising edge x parallel read from second register 1010 x ? third rising edge x parallel read from third register 1010 x ? fourth rising edge x parallel read from fourth register 1010 x ?? x ?? 1010 x ?? x ?? 1010 x ?? x ?? 1010 x ? tenth rising edge x parallel read from tenth register 1010 x ? eleventh rising edge x parallel read from first register (roll back) 1 x 1 1 x x x no operation x10x ? rising edge x x write to frame buffer memory x1x0 x ? rising edge x read from frame buffer memory 0 0 x 1 x x x illegal operation
CYFB0072V document number: 001-88646 rev. *a page 10 of 27 table 3. writing into configuration registers in serial mode spi_sen ld wen ren wclk rclk sclk operation 01xx x x ? rising edge each rising of the sclk clocks in one bit from the si (serial in). any of the 10 registers can be addressed and written to, following the spi protocol. x10x ? rising edge x x parallel write to frame buffer memory. x1x0 x ? rising edge x parallel read from frame buffer memory. 1 0 1 1 x x x this corresponds to parallel mode (refer to table 2 on page 9 ). figure 2. serial write to configuration register ld
CYFB0072V document number: 001-88646 rev. *a page 11 of 27 width expansion configuration the width of the frame buffer can be expan ded to provide word widths greater than 36 bits. during width expansion mode, all con trol line inputs are common and all flags are available. empty (full) flags are created by anding the empty (full) flags of every fr ame buffer. this technique avoids reading data from or writing data to the device that is ?staggered? by one clock cycle due to the variations in skew between rclk and wclk. figure 3 demonstrates an example of 72 bit-word wi dth by using two 36-bit word frame buffers. power up the device becomes functional after v cc1 , v cc2 , v ccio , and v ref attain minimum stable voltage required as given in recommended dc operating conditions on page 13 . the device can be accessed t pu time after these supplies attain the minimum required level (see switching characteristics on page 16 ). there is no specific power sequencing required for the device. read/write clock requirements the read and write clocks must satisfy the following requirements: both read (rclk) and write (wclk) clocks should be free-running. the clock frequency for both clocks should be between the minimum and maximum range given in electrical characteristics on page 13 . the wclk to rclk ratio should be in the range of 0.5 to 2. for proper frame buffer operation, the device must determine which of the input clocks ? rclk or wclk ? is faster. this is evaluated using counters after the mrs cycle. the device uses two 9-bit counters (one running on rclk and other on wclk), which count 256 cycles of read and write clocks after mrs . the clock of the counter which reaches its terminal count first is used as master clock inside the frame buffer. when there is change in the relative frequency of rclk and wclk during normal operation of frame buffer, user can specify it by using ?fast clk bit? in the configuration register (0xa). ?1? - indicates f req (wclk) > f req (rclk) ?0? - indicates f req (wclk) < f req (rclk) the fast clock bit configuratio n register(0xa), can be accessed by keeping ld low for 10 clock cycles. the result of counter evaluated frequency is available in this register bit. user can override the counter evaluated frequency for faster clock by changing this bit. whenever there is a change in this bit value, user must wait t pll time before issuing the next read or write to buffer memory. figure 3. width expansion ff ff ef ef write clock (wclk) write enable (wen ) ff cyf0072v cyf0072v 36 72 data in (d) 36 read clock (rclk) read enable (ren ) output enable(oe ) 36 data out (q) 36 72
CYFB0072V document number: 001-88646 rev. *a page 12 of 27 jtag operation the video frame buffer has two devices connected internally in a jtag chain as shown in figure 4 figure 4. device conn ection in a jtag chain ta b l e 4 shows the ir register length and device id device1 tdi tdo device2 tdi tdo tms tck tms tck tms tck tdi tdo trst trst table 4. jtag idcodes ir register length device id (hex) bypass register length device-1 3 ?ignore? 1 device-2 8 1e3261cf 1 table 5. jtag instructions for device-1 device-1 opcode (binary) bypass 111 table 6. jtag instructions for device-2 device-2 opcode (hex) extest 00 highz 07 sample/preload 01 bypass ff idcode 0f
CYFB0072V document number: 001-88646 rev. *a page 13 of 27 maximum ratings exceeding maximum ratings may shorten the useful life of the device. these user guidelines are not tested. storage temperature (without bias) ........ ?65 ? c to +150 ? c ambient temperature with power applied ......................................... ?55 ? c to +125 ? c core supply voltage 1 (v cc1 ) to ground potential ........................ .....................?0.3 v to 2.5 v core supply voltage 2 (v cc2 ) to ground potential ...........................................?0.3 v to 1.65 v latch up current ................................................ >100 ma i/o port supply voltage (v ccio ) ......................?0.3 v to 3.7 v voltage applied to i/o pins ...........................?0.3 v to 3.75 v output current into outputs (low) ............................. 24 ma static discharge voltage (per mil?std?883, method 3015) ......................... > 2001 v operating range range ambient temperature industrial ?40 ? c to +85 ? c recommended dc operating conditions parameter [4] description min typ max unit v cc1 core supply voltage 1 1.70 1.80 1.90 v v cc2 core supply voltage 2 1.425 1.5 1.575 v v ref reference voltage (irrespective of i/o standard used) 0.7 0.75 0.8 v v pu input cmos voltage level for the fr ame buffer lvcmos33 3.00 3.30 3.60 v lvcmos18 1.70 1.8 1.90 v v ccio i/o supply voltage, read and write banks. lvcmos33 3.00 3.30 3.60 v lvcmos18 1.70 1.8 1.90 v electrical characteristics parameter description conditions min typ max unit i cc active current v cc1 = v cc1max ??300ma v cc2 = v cc2max (all i/o switching, 133 mhz) ??600ma v ccio = v cciomax (all outputs disabled) ??100ma i i input pin leakage current v in = v cciomax to 0 v ?15 ? 15 a i oz i/o pin leakage current v o = v cciomax to 0 v ?15 ? 15 a c p capacitance for tms and tck ? ? ? 16 pf c pio capacitance for all other pins except tms and tck ? ??8pf note 4. device operation guaranteed for a supply rate > 1 v / s.
CYFB0072V document number: 001-88646 rev. *a page 14 of 27 i/o characteristics (over the operating range) i/o standard nominal i/o supply voltage input voltage (v) output voltage (v) output current (ma) v il (max) v ih (min) v ol (max) v oh (min) i ol (max) i oh (max) lvcmos33 3.3 v 0.80 2.20 0.45 2.40 24 24 lvcmos18 1.8 v 30% v ccio 65% v ccio 0.45 v ccio ? 0.45 16 16 latency table latency parameter number of cycles detail l ren _to_data 4 latency when ren is asserted low to first data output from frame buffer. l ren _to_config 4 latency when ren is asserted along with ld to first data read from configuration registers. l in max = 26 [5] initial latency for data read after frame buffer goes empty during simultaneous read/write. l ff _assert max = 4 last data write to ff going low. l ef _assert 0 last data read to ef going low. l ff _deassert 8 [5] read to ff going high. l ef _deassert max = 24 [5] write to ef going high. l prs _to_active 32 [5] prs de-assert to normal operation. l mailbox 2 latency from write port to read port when mb = 1 (w.r.t. wclk). note 5. these latency values are valid for a clock ratio of 1.
CYFB0072V document number: 001-88646 rev. *a page 15 of 27 ac test load conditions figure 5. ac test load conditions (a) v ccio = 1.8 volt (b) v ccio = 3.3 volt (c) all input pulses ? 30 0.9 v ? 30
CYFB0072V document number: 001-88646 rev. *a page 16 of 27 switching characteristics parameter description -133 unit min max t pu power-up time after all supplies reach minimum value ? 2 ms t s clock cycle frequency 3.3 v lvcmos 24 133 mhz t s clock cycle frequency 1.8 v lvcmos 24 133 mhz t a data access time ? 10 ns t clk clock cycle time 7.5 41.67 ns t clkh clock high time 3.375 ? ns t clkl clock low time 3.375 ? ns t ds data setup time 3 ? ns t dh data hold time 3 ? ns t ens enable setup time 3 ? ns t enh enable hold time 3 ? ns t ens_si setup time for spi_si and spi_sen pins 5 ? ns t enh_si hold time for spi_si and spi_sen pins 5 ? ns t rate_spi frequency of sclk ? 25 mhz t rs reset pulse width 100 ? ns t rsf reset to flag output time ? 50 ns t olz output enable to output in low z 4 15 ns t oe output enable to output valid ? 15 ns t ohz output enable to output in high z ? 15 ns t wff write clock to ff ? 8.5 ns t ref read clock to ef ? 8.5 ns t pll time required to synchronize pll ? 1024 cycles t rate_jtag jtag tck cycle time 100 ? ns t s_jtag setup time for jtag tms,tdi 8 ? ns t h_jtag hold time for jtag tms,tdi 8 ? ns t co_jtag jtag tck low to tdo valid ? 20 ns
CYFB0072V document number: 001-88646 rev. *a page 17 of 27 switching waveforms figure 6. write cycle timing figure 7. read cycle timing t clkh t clkl no operation t ds t ens wen , ie t clk t dh t enh wclk d[35:0] no operation t clk t ohz rclk ren oe t ens t olz t a t enh valid data l ren _to_data dval q[35:0]
CYFB0072V document number: 001-88646 rev. *a page 18 of 27 figure 8. reset timing figure 9. empty flag timing figure 10. full flag timing switching waveforms (continued) t rs mrs / prs t rsf t rsf t rsf oe =1 oe =0 ef ff q[35:0] dval ef ren oe rclk t ref q(last)-2 q(last)-1 q(last) invalid data q(last)-3 dval q[35:0] ef ren oe ff wclk t ds wen t wff d n-1 (written) d n (written) d n+1 (not written) d n+2 (not written) d n-2 (written) d[35:0]
CYFB0072V document number: 001-88646 rev. *a page 19 of 27 figure 11. initial data latency figure 12. flow-through mailbox operation switching waveforms (continued) l in (initial latency) d [35:0] q [35:0 wen ren rclk wclk q6 q5 q4 q1 q2 qo q3 dval t a d0 d1 d2 d3 d4 d5 d6 wclk d[35:0] ren / wen mb do d1 d3 q4 q1 q2 qo q3 q[35:0] d2 d4 dval l mailbox
CYFB0072V document number: 001-88646 rev. *a page 20 of 27 figure 13. configuration register write figure 14. configuration register read figure 15. empty flag deassertion switching waveforms (continued) ld d[35:0] config-reg 0 config-reg 1 config-reg 2 config-reg 3 config-reg 4 config-reg 5 wclk wen t ens t ds t dh rclk ren ld q[35:0] reg - 1 l ren _to_confi t a wclk rclk ren ef d [35:0] wen d0 d1 / ie l ef_deassert t ref
CYFB0072V document number: 001-88646 rev. *a page 21 of 27 figure 16. empty flag assertion figure 17. full flag assertion switching waveforms (continued) rclk ren 12345 q [35:0] q last ef dval l ren_to_data t a t ref l ff_release ff 0 1 2 3 4 wclk wen d [35:0] ff d 0 d 1 d x d last-1 d last not written not written / ie
CYFB0072V document number: 001-88646 rev. *a page 22 of 27 figure 18. full flag deassertion switching waveforms (continued) wclk wen d [35:0] ff d last-4 d last-3 d last-2 d last-1 d last rclk ren 123 8 d last-5 l ff_deassert / ie 0
CYFB0072V document number: 001-88646 rev. *a page 23 of 27 ordering code definitions ordering information speed [6] (mhz) ordering code package diagram package type operating range 133 CYFB0072V18l-133bgxi 51-85167 209-ball fbga (14 22 1.76 mm) industrial 133 CYFB0072V33l-133bgxi 51-85167 209-ball fbga (14 22 1.76 mm) industrial temperature grade: i = industrial = ?40 c to +85 c pb-free package type: bg = 209-ball fbga speed grade: 133 mhz i/o standard: l = lvcmos i/o voltage: vxx = v18 or v33 v18 = 1.8 v; v33 = 3.3 v density: 072 = 72m single queue family code: frame buffer company id: cy = cypress 072 vxx - 133 x bg l cy 0 fb i note 6. for device operating at 150-mhz, contact sales.
CYFB0072V document number: 001-88646 rev. *a page 24 of 27 package diagram figure 19. 209-ball fbga (14 22 1.76 mm) bb209a package outline, 51-85167 51-85167 *c
CYFB0072V document number: 001-88646 rev. *a page 25 of 27 acronyms document conventions units of measure acronym description ff full flag fifo first in first out ie input enable i/o input/output fbga fine-pitch ball grid array jtag joint test action group lsb least significant bit lvcmos low voltage complementary metal oxide semiconductor mb mailbox mrs master reset msb most significant bit oe output enable prs partial reset rclk read clock ren read enable rclk read clock sclk serial clock tck test clock tdi test data in tdo test data out tms test mode select wclk write clock wen write enable symbol unit of measure c degree celsius mhz megahertz ? a microampere ma milliampere mm millimeter ms millisecond ns nanosecond ? ohm pf picofarad v volt w watt
CYFB0072V document number: 001-88646 rev. *a page 26 of 27 document history page document title: CYFB0072V, 72-mbit video frame buffer document number: 001-88646 revision ecn orig. of change submission date description of change ** 4084048 smch 09/16/2013 new data sheet. *a 4136715 smch 09/26/2013 changed stat us from preliminary to final. updated features : updated the sub-features under memory organization. updated pin configuration : updated figure 1 . updated pin definitions : added v pd pin details. added note 3 and referred the same note for v ss and v pd pins. updated architecture : updated reset logic : updated description. updated programming configuration registers : updated description.
document number: 001-88646 rev. *a revised september 26, 2013 page 27 of 27 all products and company names mentioned in this document may be the trademarks of their respective holders. CYFB0072V ? cypress semiconductor corporation, 2013. the information contained herein is subject to change without notice. cypress semico nductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rig hts. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with cypres s. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a ma lfunction or failure may reasonably be expe cted to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc ? solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 4 | psoc 5lp cypress developer community community | forums | blogs | video | training technical support cypress.com/go/support

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